1. Field of the Invention
This invention relates to digital signal processors for use in digital filters and the like in which working random-access memories (i.e., working RAM or WorkRAM in abbreviation) are necessarily subjected to initialization.
This application claims priority from Japanese Patent Applications Nos. 2003-385234, 2004-240705, 2004-297983 and 2004-323735, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Conventionally, digital signal processors have been developed to perform initialization of working RAMs due to multiple processing in accordance with prescribed methods as follows:    (a) All regions of a working RAM are collectively subjected to initialization.    (b) Only a selected region of a working RAM, which is used to accumulate data in the future in order to perform processing, which have not been executed yet, is subjected to initialization.    (c) A working RAM is arranged for each group of data, which can be simultaneously initialized and thus subjected to grouping, so that initialization is performed in each unit of the working RAM.
FIG. 7 shows a three-order finite impulse response (FIR) digital filter as an applied example of a digital signal processor, that is, a digital filter 3 in which input data Din are sequentially transmitted through digital filters Rg11, Rg12, and Rg13. Herein, filtering calculations are performed by retaining input data Din at ‘0’ for a prescribed time period, which is three times longer than a sampling period T for an input signal to the digital filter 3, so that the output signal of the digital filter 3 is subjected to initialization. Suppose that a first time for transmitting input data Din to the input register Rg11, a second time for transmitting data from the input register Rg11 to the first delay register Rg12, and a third time for transmitting data from the first delay register Rg12 to the second delay register Rg13 are all set to 1 msec, wherein it is possible to initialize data respectively stored in the input register Rg11, first delay register Rg12, and second delay register Rg13 as well as the output signal of the digital filter 3 in 3 msec.
However, as to the comprehensive initialization on all regions of the working RAM, there is a problem in that prescribed data, which should not be initialized, are unexpectedly initialized, and the processing, which must run in progress, is unnecessarily stopped for a certain time period of the initialization of the working RAM.
As to the selective initialization on unused regions of the working RAM, the number of regions subjected to initialization changes in response to contents of programs executed by the digital signal processor and the number of programs being executed by the digital signal processor. Hence, it is very difficult for an engineer to directly determine the number of registers designating the overall area subjected to initialization in the digital signal processor. In addition, this increases the burden of a CPU performing processing for designating the number of regions subjected to initialization.
As to the initialization on a FIR digital filter as shown in FIG. 7, a relatively long time is required to complete the initialization, especially in the case of a high-order FIR digital filter and in the case of a FIR digital filter whose data update frequency is relatively low. As to the initialization on an IIR (infinite impulse response) digital filter, due to the existence of a feedback loop therein, the output data thereof cannot be initialized even when ‘0’ is continuously applied thereto.
As to the conventionally known high-speed initialization of memories, Japanese Patent Application Publication No. S58-34490 discloses that a prescribed command (regarding partial clearing) for clearing memory content in a specific area is used for the initialization of a display memory in display content renewing (or display refreshing), wherein the initialization is selectively performed on a specific area whose display content is changed, so that the initialization necessarily proceeds to only the specific area during operation.
Other documents such as Japanese Patent Application Publications Nos. H07-312081, H03-105640, and H04-64155 disclose the high-speed initialization of memories in which in order to increase the speed of initialization of memories in a startup mode of an apparatus, addresses are subjected to masking so as to extract groups of addresses subjected to initialization, and peripheral circuits of RAMs are reduced in sizes, thus reducing the time required for the initialization.